In addition to P to N skew requirements on the DAC clock inputs, the duty cycle of the source clock should be kept to 49/51% when applying an RF clock input. Duty cycle on the input RF clock can again limit the achievable DAC maximum sample rates. A lower duty cycle of 48/52% can be tolerated if the DAC sample rate is < 9GSPS.
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Print out the power and ground list for all ICs and check if they’re correctly connected. Print out the netlist, sort alphabetically and check for any inconsistencies (in naming, bus signals all used). This takes some time, but really can show non-obvious mistakes. Check if all capacitors are correctly de-rated for their operating voltage.
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I am using the xtp427 ultrascale-plus schematic review checklist to review my Zynq US\+MPSoC schematic. The checklist says to place 2.0kohm pull-up resistors on the SPI MISO and MOSI signals near the SPI device (with no other explanation). I cannot find any other Xilinx documents that recommend a pull-up on MISO, MOSI.
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Ultrascale GTR transceiver user guide. I have located UG576 for the GTH XCVRs, and UG578 for the GTY XCVRs, but cannot find a similar user guide for the GTR transceivers. Can someone help me locate this, or is it the exact same as the GTH (if so, I didn't see in the GTH guide that it also covers GTR). Thanks. Serial Transceiver. Share. 6 answers.
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Hello, I am trying to use the XTP427 Ultrascale\+ Schematic Review Checklist. Does anyone have a version of this that works on a 64-bit Windows machine? Thanks matt clark If you do a
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